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Ethernet and MII management
Table 25. MII management AC timing specifications (continued)
At recommended operating conditions with OV DD is 3.3 V ± 300mV.
Parameter/Condition
MDC to MDIO delay
MDIO to MDC setup time
MDIO to MDC hold time
MDC rise time
MDC fall time
Symbol 1
t MDKHDX
t MDDVKH
t MDDXKH
t MDCR
t MDHF
Min
10
8.5
0
—
—
Typical
—
—
—
—
—
Max
70
—
—
10
10
Unit
ns
ns
ns
ns
ns
Note
—
—
—
—
—
Note:
1. The symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, t MDKHDX symbolizes management
data timing (MD) for the time t MDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time.
Also, t MDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state
(V) relative to the t MDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter
convention is used with the appropriate letter: R (rise) or F (fall).
The following figure shows the MII management AC timing diagram.
MDC
t MDCH
t MDC
t MDCF
t MDCR
MDIO
(Input)
t MDDVKH
t MDDXKH
MDIO
(Output)
t MDKHDX
Figure 17. MII management interface timing diagram
8.3.3
IEEE 1588 DC Specifications
The IEEE 1588 DC timing specifications are given in the following table.
Table 26. IEEE 1588 DC Electrical Characteristics
Characteristic
Output high voltage
Output low voltage
Output low voltage
V OH
V OL
V OL
Symbol
Condition
I OH = -8.0 mA
I OL = 8.0 mA
I OL = 3.2mA
Min
2.4
—
—
Max
—
0.5
0.4
unit
V
V
V
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3
28
Freescale Semiconductor
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